Xmega Application Note | |||||
This file contains an example application that demonstrates the EBI driver. It shows how to configure the EBI for 3-port SDRAM operation. The example fills a data pattern in the memory, copies back and compares the copied block.
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Definition in file ebi_sdram_example.c.
#include "avr_compiler.h"
#include "ebi_driver.h"
Go to the source code of this file.
Defines | |
#define | MEMORY_BLOCK 1 |
Memory block to use in the memory map. | |
#define | SDRAM_ADDR (SDRAM_SIZE * MEMORY_BLOCK) |
Address where we want SDRAM to be accessed. | |
#define | SDRAM_SIZE 0x800000UL |
Size of SDRAM to be accessed. | |
#define | TESTBYTE 0xA5 |
Functions | |
int | main (void) |
Test function for EBI with SDRAM. |
#define MEMORY_BLOCK 1 |
Memory block to use in the memory map.
This depends on the size of the RAM. It can be up to (16MB/RAM_SIZE - 1). In this example the RAM size is 8MB, so the block can be either 0 or 1.
Definition at line 65 of file ebi_sdram_example.c.
#define SDRAM_ADDR (SDRAM_SIZE * MEMORY_BLOCK) |
Address where we want SDRAM to be accessed.
Definition at line 68 of file ebi_sdram_example.c.
Referenced by main().
#define SDRAM_SIZE 0x800000UL |
#define TESTBYTE 0xA5 |
int main | ( | void | ) |
Test function for EBI with SDRAM.
Hardware setup for 3-port SDRAM interface:
PORTK[7:0] - A[7:0]
PORTJ[7:0] - {A[11:8],D[3:0]}
PORTH[7:0] - {WE,CAS,RAS,DQM,BA0,BA1,CKE,CLK}
Since the EBI in 3-port mode does not have any spare pins for Chip Select, this should be controlled by a General Purpose IO pin or be pulled low by externally to enable the RAM.
The EBI SDRAM settings need to be set according to the characteristics of the SDRAM in use. The settings for used with the SDRAM in this example is commented in the EBI_EnableSDRAM function call.
The setup is tested by writing a set of data to the SDRAM. The data is then read back and verified. At the end, the program will be stuck in one of two infinite loops, dependent on whether the test passed or not.
Definition at line 93 of file ebi_sdram_example.c.
References EBI_Enable(), EBI_EnableSDRAM(), SDRAM_ADDR, and TESTBYTE.
00094 { 00095 /* Counter indicating correct data transfer to and from SDRAM */ 00096 uint32_t SDRAM_ERR = 0; 00097 00098 /* Configure bus pins as outputs(except for data lines). */ 00099 PORTH.DIR = 0xFF; 00100 PORTK.DIR = 0xFF; 00101 PORTJ.DIR = 0xF0; 00102 00103 /* Initialize EBI. */ 00104 EBI_Enable( EBI_SDDATAW_4BIT_gc, 00105 EBI_LPCMODE_ALE1_gc, 00106 EBI_SRMODE_ALE12_gc, 00107 EBI_IFMODE_3PORT_gc ); 00108 00109 /* Initialize SDRAM. (PER2X clock is 2MHz giving a 500ns clock cycle.) */ 00110 EBI_EnableSDRAM( EBI_CS_ASPACE_8MB_gc, /* 8 MB address space. */ 00111 SDRAM_ADDR, /* Base address. */ 00112 false, /* 2 cycle CAS Latency. */ 00113 true, /* 12 Row bits. */ 00114 EBI_SDCOL_10BIT_gc, /* 10 Column bits. */ 00115 EBI_MRDLY_2CLK_gc, /* 2 cycle Mode Register Delay. (min 2CLK) */ 00116 EBI_ROWCYCDLY_1CLK_gc, /* 1 cycle Row Cycle Delay. */ 00117 EBI_RPDLY_1CLK_gc, /* 1 cycle Row to Pre-charge Delay. (min 37ns) */ 00118 EBI_WRDLY_2CLK_gc, /* 2 cycle Write Recovery Delay. (1CLK + 7ns)*/ 00119 EBI_ESRDLY_1CLK_gc, /* 1 cycle Exit Self Refresh to Active Delay. (min 67ns) */ 00120 EBI_ROWCOLDLY_1CLK_gc, /* 1 cycle Row to Column Delay. (min 15ns) */ 00121 0x001F, /* 31 cycle Refresh Period (max 15.625us). */ 00122 0x00C8 ); /* 200 cycle Initialization Delay (min 100us). */ 00123 00124 /* Fill SDRAM with data. */ 00125 for (uint32_t i = 0; i < 0x40000; i++) { 00126 __far_mem_write(i+SDRAM_ADDR, TESTBYTE); 00127 } 00128 00129 /* Read back from SDRAM and verify. */ 00130 for (uint32_t i = 0; i < 0x40000; i++) { 00131 if (__far_mem_read(i+SDRAM_ADDR) != TESTBYTE){ 00132 SDRAM_ERR++; 00133 } 00134 } 00135 00136 /* Report success or failure. */ 00137 00138 if (SDRAM_ERR == 0) { 00139 while(true) { 00140 /* Breakpoint for success. */ 00141 nop(); 00142 } 00143 } 00144 else { 00145 while(true) { 00146 /* Breakpoint for failure. */ 00147 nop(); 00148 } 00149 } 00150 }
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