XMEGA Application Note | |||||
00001 /* This file has been prepared for Doxygen automatic documentation generation.*/ 00062 #include "avr_compiler.h" 00063 #include "ccpwrite.h" 00064 #include "sleepmgr.h" 00065 #include "lowpower.h" 00066 #include "rtc_driver.h" 00067 00069 #define RTC_PERIOD 8 00070 00072 // #define RTC_XTAL 00073 00075 #ifndef F_CPU 00076 #define F_CPU 2000000 00077 #endif // F_CPU 00078 00079 00081 uint8_t gState = 0; 00082 00083 00091 int main(void) 00092 { 00093 // Initialize device to the least power consuming state. 00094 LOWPOWER_Init(); 00095 00096 // Enable EEPROM and Flash power reduction mode. 00097 CCPWrite(&NVM.CTRLB, NVM_EPRM_bm | NVM_FPRM_bm); 00098 00099 // Initialize the sleep manager. 00100 SLEEPMGR_Init(); 00101 00102 // Clear bit for RTC in PRR because it is set by LOWPOWER_Init(). 00103 PR.PRGEN &= ~PR_RTC_bm; 00104 00105 // Use ULP as clock source for RTC if RTC_XTAL is not defined. 00106 #ifndef RTC_XTAL 00107 // Set internal 32kHz ULP oscillator as clock source for RTC. 00108 CLK.RTCCTRL = CLK_RTCSRC_ULP_gc | CLK_RTCEN_bm; 00109 #else 00110 // Enable external 32 kHz XTAL oscillator in low-power mode. 00111 OSC.XOSCCTRL = OSC_XOSCSEL_32KHz_gc | OSC_X32KLPM_bm; 00112 OSC.CTRL |= OSC_XOSCEN_bm; 00113 00114 // Wait for oscillator to stabilize before setting as RTC clock source. 00115 do { } while (!( OSC.STATUS & OSC_XOSCRDY_bm )); 00116 CLK.RTCCTRL = CLK_RTCSRC_TOSC_gc | CLK_RTCEN_bm; 00117 #endif // RTC_XTAL 00118 00119 // Wait until RTC is ready. 00120 do { } while ( RTC_Busy() ); 00121 00122 // Configure RTC wakeup period. 00123 RTC_Initialize( RTC_PERIOD, 0, RTC_PERIOD-1, RTC_PRESCALER_DIV1024_gc ); 00124 00125 // Enable RTC compare interrupts. 00126 RTC_SetCompareIntLevel( RTC_COMPINTLVL_LO_gc ); 00127 PMIC.CTRL |= PMIC_LOLVLEN_bm; 00128 sei(); 00129 00130 // The device should first spend time in ACTIVE, so wait for 00131 // the RTC compare ISR to change the state. 00132 do { } while(gState == 0); 00133 00134 // Disable Flash power reduction mode due to errata. 00135 // (The device will spend most of its time in sleep from now on, so we 00136 // won't bother clearing/setting FPRM before and after sleep.) 00137 CCPWrite(&NVM.CTRLB, NVM_EPRM_bm); 00138 00139 // Go to sleep. The RTC compare ISR configures the sleep modes. 00140 do { 00141 SLEEPMGR_Sleep(); 00142 } while (1); 00143 } 00144 00145 00151 ISR(RTC_COMP_vect) 00152 { 00153 switch(gState) { 00154 // The device starts out in active mode. Go to Idle. 00155 case 0: 00156 SLEEPMGR_Lock( SLEEPMGR_IDLE ); 00157 ++gState; 00158 break; 00159 00160 // Power-save follows after Idle. 00161 case 1: 00162 SLEEPMGR_Unlock( SLEEPMGR_IDLE ); 00163 SLEEPMGR_Lock( SLEEPMGR_SAVE ); 00164 ++gState; 00165 break; 00166 00167 // Power-down follows after Power-save. The device won't wake up again. 00168 case 2: 00169 SLEEPMGR_Unlock( SLEEPMGR_SAVE ); 00170 SLEEPMGR_Lock( SLEEPMGR_DOWN ); 00171 ++gState; 00172 break; 00173 00174 // Shouldn't end up here.. Go to Idle. 00175 default: 00176 SLEEPMGR_Init(); 00177 SLEEPMGR_Lock( SLEEPMGR_IDLE ); 00178 gState = 1; 00179 } 00180 }
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