Xmega Application Note


clksys_driver.c

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00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00067 #include "clksys_driver.h"
00068 
00077 void CCPWrite( volatile uint8_t * address, uint8_t value )
00078 {
00079 #ifdef __ICCAVR__
00080 
00081         // Store global interrupt setting in scratch register and disable interrupts.
00082         asm("in  R1, 0x3F \n"
00083             "cli"
00084             );
00085 
00086         // Move destination address pointer to Z pointer registers.
00087         asm("movw r30, r16");
00088 #ifdef RAMPZ
00089         asm("ldi  R16, 0 \n"
00090             "out  0x3B, R16"
00091             );
00092 
00093 #endif
00094         asm("ldi  r16,  0xD8 \n"
00095             "out  0x34, r16  \n"
00096 #if (__MEMORY_MODEL__ == 1)
00097             "st     Z,  r17  \n");
00098 #elif (__MEMORY_MODEL__ == 2)
00099             "st     Z,  r18  \n");
00100 #else /* (__MEMORY_MODEL__ == 3) || (__MEMORY_MODEL__ == 5) */
00101             "st     Z,  r19  \n");
00102 #endif /* __MEMORY_MODEL__ */
00103 
00104         // Restore global interrupt setting from scratch register.
00105         asm("out  0x3F, R1");
00106 
00107 #elif defined __GNUC__
00108         AVR_ENTER_CRITICAL_REGION( );
00109         volatile uint8_t * tmpAddr = address;
00110 #ifdef RAMPZ
00111         RAMPZ = 0;
00112 #endif
00113         asm volatile(
00114                 "movw r30,  %0"       "\n\t"
00115                 "ldi  r16,  %2"       "\n\t"
00116                 "out   %3, r16"       "\n\t"
00117                 "st     Z,  %1"       "\n\t"
00118                 :
00119                 : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP)
00120                 : "r16", "r30", "r31"
00121                 );
00122 
00123         AVR_LEAVE_CRITICAL_REGION( );
00124 #endif
00125 }
00126 
00141 void CLKSYS_XOSC_Config( OSC_FRQRANGE_t freqRange,
00142                          bool lowPower32kHz,
00143                          OSC_XOSCSEL_t xoscModeSelection )
00144 {
00145         OSC.XOSCCTRL = (uint8_t) freqRange |
00146                        ( lowPower32kHz ? OSC_X32KLPM_bm : 0 ) |
00147                        xoscModeSelection;
00148 }
00149 
00150 
00167 void CLKSYS_PLL_Config( OSC_PLLSRC_t clockSource, uint8_t factor )
00168 {
00169         factor &= OSC_PLLFAC_gm;
00170         OSC.PLLCTRL = (uint8_t) clockSource | ( factor << OSC_PLLFAC_gp );
00171 }
00172 
00173 
00187 uint8_t CLKSYS_Disable( uint8_t oscSel )
00188 {
00189         OSC.CTRL &= ~oscSel;
00190         uint8_t clkEnabled = OSC.CTRL & oscSel;
00191         return clkEnabled;
00192 }
00193 
00194 
00206 void CLKSYS_Prescalers_Config( CLK_PSADIV_t PSAfactor,
00207                                CLK_PSBCDIV_t PSBCfactor )
00208 {
00209         uint8_t PSconfig = (uint8_t) PSAfactor | PSBCfactor;
00210         CCPWrite( &CLK.PSCTRL, PSconfig );
00211 }
00212 
00213 
00225 uint8_t CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_t clockSource )
00226 {
00227         uint8_t clkCtrl = ( CLK.CTRL & ~CLK_SCLKSEL_gm ) | clockSource;
00228         CCPWrite( &CLK.CTRL, clkCtrl );
00229         clkCtrl = ( CLK.CTRL & clockSource );
00230         return clkCtrl;
00231 }
00232 
00233 
00241 void CLKSYS_RTC_ClockSource_Enable( CLK_RTCSRC_t clockSource )
00242 {
00243         CLK.RTCCTRL = ( CLK.RTCCTRL & ~CLK_RTCSRC_gm ) |
00244                       clockSource |
00245                       CLK_RTCEN_bm;
00246 }
00247 
00248 
00260 void CLKSYS_AutoCalibration_Enable( uint8_t clkSource, bool extReference )
00261 {
00262         OSC.DFLLCTRL = ( OSC.DFLLCTRL & ~clkSource ) |
00263                        ( extReference ? clkSource : 0 );
00264         if (clkSource == OSC_RC2MCREF_bm) {
00265                 DFLLRC2M.CTRL |= DFLL_ENABLE_bm;
00266         } else if (clkSource == OSC_RC32MCREF_bm) {
00267                 DFLLRC32M.CTRL |= DFLL_ENABLE_bm;
00268         }
00269 }
00270 
00271 
00280 void CLKSYS_XOSC_FailureDetection_Enable( void )
00281 {
00282         CCPWrite( &OSC.XOSCFAIL, ( OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm ) );
00283 }
00284 
00285 
00292 void CLKSYS_Configuration_Lock( void )
00293 {
00294         CCPWrite( &CLK.LOCK, CLK_LOCK_bm );
00295 }
00296 
@DOC_TITLE@
Generated on Mon Sep 14 09:48:09 2009 for AVR1003 Using the XMEGA Clock System by doxygen 1.5.8