00001
00067 #include "clksys_driver.h"
00068
00077 void CCPWrite( volatile uint8_t * address, uint8_t value )
00078 {
00079 #ifdef __ICCAVR__
00080 asm("movw r30, r16");
00081 #ifdef RAMPZ
00082 RAMPZ = 0;
00083 #endif
00084 asm("ldi r16, 0xD8 \n"
00085 "out 0x34, r16 \n"
00086 "st Z, r18 \n");
00087
00088 #elif defined __GNUC__
00089 volatile uint8_t * tmpAddr = address;
00090 #ifdef RAMPZ
00091 RAMPZ = 0;
00092 #endif
00093 asm volatile(
00094 "movw r30, %0" "\n\t"
00095 "ldi r16, %2" "\n\t"
00096 "out %3, r16" "\n\t"
00097 "st Z, %1"
00098 :
00099 : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "m" (CCP)
00100 : "r16", "r30", "r31"
00101 );
00102
00103 #endif
00104 }
00105
00120 void CLKSYS_XOSC_Config( OSC_FRQRANGE_t freqRange,
00121 bool lowPower32kHz,
00122 OSC_XOSCSEL_t xoscModeSelection )
00123 {
00124 OSC.XOSCCTRL = (uint8_t) freqRange |
00125 ( lowPower32kHz ? OSC_X32KLPM_bm : 0 ) |
00126 xoscModeSelection;
00127 }
00128
00129
00146 void CLKSYS_PLL_Config( OSC_PLLSRC_t clockSource, uint8_t factor )
00147 {
00148 factor &= OSC_PLLFAC_gm;
00149 OSC.PLLCTRL = (uint8_t) clockSource | ( factor << OSC_PLLFAC_gp );
00150 }
00151
00152
00166 uint8_t CLKSYS_Disable( uint8_t oscSel )
00167 {
00168 OSC.CTRL &= ~oscSel;
00169 uint8_t clkEnabled = OSC.CTRL & oscSel;
00170 return clkEnabled;
00171 }
00172
00173
00185 void CLKSYS_Prescalers_Config( CLK_PSADIV_t PSAfactor,
00186 CLK_PSBCDIV_t PSBCfactor )
00187 {
00188 uint8_t PSconfig = (uint8_t) PSAfactor | PSBCfactor;
00189 CCPWrite( &CLK.PSCTRL, PSconfig );
00190 }
00191
00192
00204 uint8_t CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_t clockSource )
00205 {
00206 uint8_t clkCtrl = ( CLK.CTRL & ~CLK_SCLKSEL_gm ) | clockSource;
00207 CCPWrite( &CLK.CTRL, clkCtrl );
00208 clkCtrl = ( CLK.CTRL & clockSource );
00209 return clkCtrl;
00210 }
00211
00212
00220 void CLKSYS_RTC_ClockSource_Enable( CLK_RTCSRC_t clockSource )
00221 {
00222 CLK.RTCCTRL = ( CLK.RTCCTRL & ~CLK_RTCSRC_gm ) |
00223 clockSource |
00224 CLK_RTCEN_bm;
00225 }
00226
00227
00239 void CLKSYS_AutoCalibration_Enable( uint8_t clkSource, bool extReference )
00240 {
00241 OSC.DFLLCTRL = ( OSC.DFLLCTRL & ~clkSource ) |
00242 ( extReference ? clkSource : 0 );
00243 if (clkSource == OSC_RC2MCREF_bm) {
00244 DFLLRC2M.CTRL |= DFLL_ENABLE_bm;
00245 } else if (clkSource == OSC_RC32MCREF_bm) {
00246 DFLLRC32M.CTRL |= DFLL_ENABLE_bm;
00247 }
00248 }
00249
00250
00259 void CLKSYS_XOSC_FailureDetection_Enable( void )
00260 {
00261 CCPWrite( &OSC.XOSCFAIL, ( OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm ) );
00262 }
00263
00264
00271 void CLKSYS_Configuration_Lock( void )
00272 {
00273 CCPWrite( &CLK.LOCK, CLK_LOCK_bm );
00274 }
00275