00001
00059 #ifndef EBI_DRIVER_H
00060 #define EBI_DRIVER_H
00061
00062 #include "avr_compiler.h"
00063
00064 #if defined( __GNUC__ )
00065
00078 #define __far_mem_read(addr) \
00079 (__extension__({ \
00080 uint32_t temp32 = (uint32_t)(addr); \
00081 uint8_t result; \
00082 asm volatile( \
00083 "in __tmp_reg__, %2" "\n\t" \
00084 "out %2, %C1" "\n\t" \
00085 "movw r30, %1" "\n\t" \
00086 "ld %0, Z" "\n\t" \
00087 "out %2, __tmp_reg__" "\n\t" \
00088 : "=r" (result) \
00089 : "r" (temp32), \
00090 "I" (_SFR_IO_ADDR(RAMPZ)) \
00091 : "r30", "r31" \
00092 ); \
00093 result; \
00094 }))
00095
00096 #define __far_mem_write(addr, data) \
00097 (__extension__({ \
00098 uint32_t temp32 = (uint32_t)(addr); \
00099 asm volatile( \
00100 "in __tmp_reg__, %1" "\n\t" \
00101 "out %1, %C0" "\n\t" \
00102 "movw r30, %0" "\n\t" \
00103 "st Z, %2" "\n\t" \
00104 "out %1, __tmp_reg__" \
00105 : \
00106 : "r" (temp32), \
00107 "I" (_SFR_IO_ADDR(RAMPZ)), \
00108 "r" ((uint8_t)data) \
00109 : "r30", "r31" \
00110 ); \
00111 }))
00112
00113 #define _far_mem_enter_ISR() uint8_t volatile saved_rampz = RAMPZ; \
00114 RAMPZ = 0;
00115
00116 #define __far_mem_exit_ISR() RAMPZ = saved_rampz;
00117
00118 #elif defined( __ICCAVR__ )
00119
00124 #define __far_mem_write(addr, data) ((__huge uint8_t *) 0x00)[addr] = data
00125 #define __far_mem_read(addr) ((__huge uint8_t *) 0x00)[addr]
00126 #endif
00127
00128
00129
00130
00136 #define EBI_Disable() (EBI.CTRL = EBI.CTRL & ~EBI_IFMODE_gm | EBI_IFMODE_DISABLED_gc)
00137
00138
00139
00146 #define EBI_DisableChipSelect(_chipSelect) ( (_chipSelect)->CTRLA = (_chipSelect)->CTRLA & ~EBI_CS_MODE_gm | EBI_CS_MODE_DISABLED_gc )
00147
00148
00149
00157 #define EBI_SetSDRAMMode(_sdramMode) ( EBI.CS3.CTRLB = EBI.CS3.CTRLB & ~EBI_CS_SDMODE_gm | (_sdramMode) )
00158
00159
00160
00167 #define EBI_EnableSelfRefresh() (EBI.CS3.CTRLB |= EBI_CS_SDSREN_bm)
00168
00169
00170
00176 #define EBI_DisableSelfRefresh() (EBI.CS3.CTRLB &= ~EBI_CS_SDSREN_bm)
00177
00178
00179
00180
00181
00182 void EBI_Enable( EBI_SDDATAW_t sdramDataWidth,
00183 EBI_LPCMODE_t lpcMode,
00184 EBI_SRMODE_t sramMode,
00185 EBI_IFMODE_t interfaceMode );
00186
00187 void EBI_EnableSRAM( volatile EBI_CS_t * chipSelect,
00188 EBI_CS_ASPACE_t addrSpace,
00189 uint32_t baseAddr,
00190 uint8_t waitStateCycles );
00191
00192 void EBI_EnableLPC( volatile EBI_CS_t * chipSelect,
00193 EBI_CS_ASPACE_t addrSpace,
00194 uint32_t baseAddr,
00195 uint8_t waitStateCycles );
00196
00197 void EBI_EnableSDRAM( EBI_CS_ASPACE_t addrSpace,
00198 uint32_t baseAddr,
00199 bool casLatency,
00200 bool rowBits,
00201 EBI_SDCOL_t columnBits,
00202 EBI_MRDLY_t modeRegisterDelay,
00203 EBI_ROWCYCDLY_t rowCycleDelay,
00204 EBI_RPDLY_t rowToPrechargeDelay,
00205 EBI_WRDLY_t writeRecoveryDelay,
00206 EBI_ESRDLY_t exitSelfRefreshToActiveDelay,
00207 EBI_ROWCOLDLY_t rowToColumnDelay,
00208 uint16_t refreshPeriod,
00209 uint16_t initializationDelay );
00210
00211 #endif