00001
00067 #include "ebi_driver.h"
00068
00069
00085 void EBI_Enable( EBI_SDDATAW_t sdramDataWidth,
00086 EBI_LPCMODE_t lpcMode,
00087 EBI_SRMODE_t sramMode,
00088 EBI_IFMODE_t interfaceMode )
00089 {
00090
00091 EBI.CTRL = (uint8_t) sdramDataWidth | lpcMode | sramMode | interfaceMode;
00092 }
00093
00094
00095
00105 void EBI_EnableSRAM( volatile EBI_CS_t * chipSelect,
00106 EBI_CS_ASPACE_t addrSpace,
00107 uint32_t baseAddr,
00108 uint8_t waitStateCycles )
00109 {
00110
00111 chipSelect->CTRLB = (chipSelect->CTRLB & ~EBI_CS_SRWS_gm) |
00112 (waitStateCycles & EBI_CS_SRWS_gm);
00113
00114
00115 chipSelect->BASEADDR = (((uint32_t) baseAddr)>>8) & (0xFFFF<<(addrSpace>>2));
00116
00117
00118 chipSelect->CTRLA = (chipSelect->CTRLA & ~(EBI_CS_ASPACE_gm | EBI_CS_MODE_gm)) |
00119 addrSpace | EBI_CS_MODE_SRAM_gc;
00120 }
00121
00122
00123
00133 void EBI_EnableLPC( volatile EBI_CS_t * chipSelect,
00134 EBI_CS_ASPACE_t addrSpace,
00135 uint32_t baseAddr,
00136 uint8_t waitStateCycles )
00137 {
00138
00139 chipSelect->CTRLB = (chipSelect->CTRLB & ~EBI_CS_SRWS_gm) |
00140 (waitStateCycles & EBI_CS_SRWS_gm);
00141
00142
00143 chipSelect->BASEADDR = (((uint32_t) baseAddr)>>8) & (0xFFFF<<(addrSpace>>2));
00144
00145
00146 chipSelect->CTRLA = (chipSelect->CTRLA & ~(EBI_CS_ASPACE_gm | EBI_CS_MODE_gm)) |
00147 addrSpace | EBI_CS_MODE_LPC_gc;
00148 }
00149
00150
00151
00171 void EBI_EnableSDRAM( EBI_CS_ASPACE_t addrSpace,
00172 uint32_t baseAddr,
00173 bool casLatency,
00174 bool rowBits,
00175 EBI_SDCOL_t columnBits,
00176 EBI_MRDLY_t modeRegisterDelay,
00177 EBI_ROWCYCDLY_t rowCycleDelay,
00178 EBI_RPDLY_t rowToPrechargeDelay,
00179 EBI_WRDLY_t writeRecoveryDelay,
00180 EBI_ESRDLY_t exitSelfRefreshToActiveDelay,
00181 EBI_ROWCOLDLY_t rowToColumnDelay,
00182 uint16_t refreshPeriod,
00183 uint16_t initializationDelay )
00184 {
00185
00186 EBI.SDRAMCTRLA = (EBI.SDRAMCTRLA & ~(EBI_SDCAS_bm | EBI_SDROW_bm | EBI_SDCOL_gm)) |
00187 (casLatency ? EBI_SDCAS_bm : 0) | (rowBits ? EBI_SDROW_bm : 0) | columnBits;
00188
00189
00190 EBI.SDRAMCTRLB = (uint8_t) modeRegisterDelay | rowCycleDelay | rowToPrechargeDelay;
00191 EBI.SDRAMCTRLC = (uint8_t) writeRecoveryDelay | exitSelfRefreshToActiveDelay | rowToColumnDelay;
00192
00193
00194 EBI.REFRESH = refreshPeriod & 0x03FF;
00195 EBI.INITDLY = initializationDelay & 0x3FFF;
00196
00197
00198 EBI.CS3.CTRLB = (EBI.CS3.CTRLB & ~(EBI_CS_SDSREN_bm | EBI_CS_SDMODE_gm)) |
00199 EBI_CS_SDMODE_NORMAL_gc;
00200
00201
00202 EBI.CS3.BASEADDR = (((uint32_t) baseAddr)>>8) & (0xFFFF<<(addrSpace>>2));
00203
00204 EBI.CS3.CTRLA = (EBI.CS3.CTRLA & ~(EBI_CS_ASPACE_gm | EBI_CS_MODE_gm)) |
00205 addrSpace | EBI_CS_MODE_SDRAM_gc;
00206
00207
00208 while ((EBI.CS3.CTRLB & EBI_CS_SDINITDONE_bm) == 0){
00209
00210 }
00211 }