Xmega Application Note


ebi_sdram_example.c

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00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00051 #include "avr_compiler.h"
00052 #include "ebi_driver.h"
00053 
00054 /* \brief Define the testbyte to be written to the RAM. */
00055 #define TESTBYTE   0xA5
00056 
00058 #define SDRAM_SIZE 0x800000UL
00059 
00065 #define MEMORY_BLOCK 1
00066 
00068 #define SDRAM_ADDR (SDRAM_SIZE * MEMORY_BLOCK)
00069 
00070 
00093 int main( void )
00094 {
00095         /* Counter indicating correct data transfer to and from SDRAM */
00096         uint32_t SDRAM_ERR = 0;
00097 
00098         /* Configure bus pins as outputs(except for data lines). */
00099         PORTH.DIR = 0xFF;
00100         PORTK.DIR = 0xFF;
00101         PORTJ.DIR = 0xF0;
00102 
00103         /* Initialize EBI. */
00104         EBI_Enable( EBI_SDDATAW_4BIT_gc,
00105                     EBI_LPCMODE_ALE1_gc,
00106                     EBI_SRMODE_ALE12_gc,
00107                     EBI_IFMODE_3PORT_gc );
00108 
00109         /* Initialize SDRAM. (PER2X clock is 2MHz giving a 500ns clock cycle.) */
00110         EBI_EnableSDRAM( EBI_CS_ASPACE_8MB_gc,   /* 8 MB address space. */
00111                          SDRAM_ADDR,             /* Base address. */
00112                          false,                  /* 2 cycle CAS Latency. */
00113                          true,                   /* 12 Row bits. */
00114                          EBI_SDCOL_10BIT_gc,     /* 10 Column bits. */
00115                          EBI_MRDLY_2CLK_gc,      /* 2 cycle Mode Register Delay. (min 2CLK) */
00116                          EBI_ROWCYCDLY_1CLK_gc,  /* 1 cycle Row Cycle Delay. */
00117                          EBI_RPDLY_1CLK_gc,      /* 1 cycle Row to Pre-charge Delay. (min 37ns) */
00118                          EBI_WRDLY_2CLK_gc,      /* 2 cycle Write Recovery Delay. (1CLK + 7ns)*/
00119                          EBI_ESRDLY_1CLK_gc,     /* 1 cycle Exit Self Refresh to Active Delay. (min 67ns) */
00120                          EBI_ROWCOLDLY_1CLK_gc,  /* 1 cycle Row to Column Delay. (min 15ns) */
00121                          0x001F,                 /* 31 cycle Refresh Period (max 15.625us). */
00122                          0x00C8 );               /* 200 cycle Initialization Delay (min 100us). */
00123 
00124         /* Fill SDRAM with data. */
00125         for (uint32_t i = 0; i < 0x40000; i++) {
00126                 __far_mem_write(i+SDRAM_ADDR, TESTBYTE);
00127         }
00128 
00129         /* Read back from SDRAM and verify. */
00130         for (uint32_t i = 0; i < 0x40000; i++) {
00131                 if (__far_mem_read(i+SDRAM_ADDR) != TESTBYTE){
00132                         SDRAM_ERR++;
00133                 }
00134         }
00135 
00136         /* Report success or failure. */
00137 
00138         if (SDRAM_ERR == 0) {
00139                 while(true) {
00140                 /* Breakpoint for success. */
00141                         nop();
00142                 }
00143         }
00144         else {
00145                 while(true) {
00146                 /* Breakpoint for failure. */
00147                         nop();
00148                 }
00149         }
00150 }
@DOC_TITLE@
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